The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to structure and method for row decoded biasing of sense amplifiers for improved one""s margin.
Modem electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory device. The memory device stores data in vast arrays of memory cells. Each cell conventionally stores a single bit of data (a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d) and can be individually accessed or addressed. Data is output from a memory cell during a xe2x80x9creadxe2x80x9d operation, and data is stored into a memory cell during a xe2x80x9cwritexe2x80x9d operation.
In a standard read or write operation, a column decoder and a row decoder translate address signals into a single intersection of a row (wordline) and column (digitline, or bitline) within the memory array. This function permits the memory cell at that location to be read from or for data to be placed into that cell. The processing of data is dependent on the time it takes to store or retrieve individual bits of data in the memory cells. Storing and retrieving the bits of data is controlled generally by a microprocessor, whereby data is passed to and from the memory array through a fixed number of input/output (I/O) lines and I/O pins. According to current processing technology the accuracy of sensing data is further dependent on the magnitude of charge stored in a memory cell and the capacitance inherent in the integrated circuit. Typically a logical xe2x80x9c1xe2x80x9d is stored in a memory cell as Vcc on a storage node side of a capacitor with a potential of Vcc/2 on the common plate of the memory cell capacitor. The capacitor is on the order of 25 femto Farads (fF). When reading the xe2x80x9c1xe2x80x9d from the capacitor the row line turns on the access transistor between the storage node side of the capacitor and the digit line. The digit line was precharged to Vcc/2 and has a capacitance on the order of 150 to 200 fF. The charge from the storage node dumps onto the digit line and brings its voltage up slightly above the equilibrate level of Vcc/2. Here, +Vcc/2 means a voltage signal slightly greater than Vcc/2, e.g. Vcc/2 plus 50 mV. The reason that the cell only brings the digit up slightly is because of the digit lines large capacitance with respect to the cell. Or to put it another way, the same charge that gets the storage node of the cell to Vcc can only move the digit lines slightly above their equilibrate level of Vcc/2.
When looking at a xe2x80x9c0xe2x80x9d dumping onto a digitline the same principals apply. Even though the storage node side of the cell is at ground when the row line turns on the access gate to that cell, very little charge from the digitline is needed to get the digitline and cell at the same level. This new level is slightly lower than the digitline""s equilibrated level of Vcc/2. In this case, xe2x88x92Vcc/2 will be a voltage signal which is slightly less than Vcc/2, e.g. Vcc/2 minus 50 mV.
A sense amplifier uses the difference between the digitline seeing the cell dump onto it versus the other digitline that remains at the equilibrated level to determine which line to pull up to Vcc and which one to pull down to ground. The accuracy of the sensing operation is thus dependent on the signal clarity between sensing +Vcc/2 and xe2x88x92Vcc/2.
The magnitude of charge required to store a logical xe2x80x9c1,xe2x80x9d and the rate at which that charge has to be refreshed, contribute to additional operational burdens on the integrated circuit as a whole. Modern applications call on electronic systems to use less power and to process data at greater speeds. In order for electronic systems to meet to these demands, the sensing operation must advance in speed and accuracy.
One method to advance the sensing operation is to bias the sense amplifier in one direction or another, e.g., to favor reading a logical xe2x80x9c1xe2x80x9d over a logical xe2x80x9c0.xe2x80x9dNormally, biasing of a sense amplifier is unintentional. When it occurs unintentionally, the sense amplifier affected will tend to fire in the same direction every time, which helps some of the bits on the column and hurts others. Since a logical xe2x80x9c1xe2x80x9d signal is sometimes weak, the sensing operation may mis-detect an ambiguous logical xe2x80x9c1xe2x80x9d signal as a logical xe2x80x9c0.xe2x80x9d To correct for such error, it is desirable to favor sensing a logical xe2x80x9c1xe2x80x9d over the sensing of a logical xe2x80x9c0.xe2x80x9d This is done by increasing the signal response range for a logical xe2x80x9c1.xe2x80x9d Commonly, this is referred to as trading the xe2x80x9czero""s marginxe2x80x9d for the xe2x80x9cone""s margin.xe2x80x9d One method of favoring logical xe2x80x9c1xe2x80x9d is by adjusting the digitline equilibrate level. However the equilibration time, which is known as tRP time, is getting too short to allow the digitlines to move from their initial equilibration of Vcc/2.
In example, during equilibration we first short digitline (DIG) and digitline* (DIG*) together. Since one was at Vcc and the other at ground, they both end up at Vcc/2. The digitlines need to be then supplied with a Vcc/2 voltage or they would eventually leak away to ground. This voltage however cannot be supplied directly to the digitlines because any row to column shorts would cause too much current during standby. To combat this effect, Vcc/2 is supplied through a long L n-channel which has high resistance and limits the amount of current that a row to column short can cause. The high resistance also means that it takes a while to get the digitlines to a voltage other than Vcc/2 during the equilibration time. Otherwise stated, it takes a while to get the digitlines to a voltage other than Vcc/2 before the next read in the same memory subarray occurs. This method of trading xe2x80x9czero""s marginxe2x80x9d for the xe2x80x9cone""s marginxe2x80x9d is being abandoned for this reason. Also, adjusting Vcc/2 to other values causes the margin to vary with cycle time.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop better methods to improve the data sensing operation without an increase in the operational cycle times.
The above mentioned problems with the sense amplifier operation in memory circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method which accords improved benefits is provided.
In particular, an illustrative embodiment of the present invention includes taking the predecoded the row address signals (i.e. RA123 less than n greater than , LPHe less than n greater than , LPHo less than n greater than ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a xe2x80x9csensedxe2x80x9d logical xe2x80x9c1xe2x80x9d on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0,xe2x80x9d the biasing will cause the sense amplifier to read a logical xe2x80x9c1xe2x80x9d.
A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross couple n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical xe2x80x9c1xe2x80x9d. In an exemplary embodiment, the two RNL*s run up the sense amplifier gap in a six square features (6F2) memory cell layout architecture with vertical twist. In this layout, double twisted columns go to one sense amplifier gap and single twisted columns go to the other sense amplifier gap. Every sense amplifier in a particular gap gets connected up the same way. Only the local phase is needed to tell which digitline is getting the signal, or charge, and which is the reference digitline.
The improved structure and method provides a greater, or expanded, signal detection range representing a logical xe2x80x9c1.xe2x80x9d In other words, the margin for detecting a logical xe2x80x9c1,xe2x80x9d or xe2x80x9cone""s margin,xe2x80x9d is increased. A margin, or portion, of the signal detecting range traditionally allotted for logical xe2x80x9c0xe2x80x9d is required to expand the xe2x80x9cone""s margin.xe2x80x9d The expanded logical xe2x80x9c1xe2x80x9d signal detection range allows the voltage level in the xe2x80x9csensedxe2x80x9d cell to fall as far down as the digitline equilibrated value of Vcc/2 (also referred to as DVC2) before it will fail to read out as a logical xe2x80x9c1.xe2x80x9d However, the accuracy of detecting a logical xe2x80x9c0xe2x80x9d is not significantly restricted.
Another notable advantage to the present invention is that favoring a logical xe2x80x9c1xe2x80x9d in the sensing operation requires less charge to store a logical xe2x80x9c1xe2x80x9d in a memory cell. This helps to reduce the negative effects of capacitive coupling between the digitlines and other memory cells in the memory array.
Still another advantage of the present invention is that the circuit design reduces charge leakage rate to a logical xe2x80x9c1xe2x80x9d in the memory cell. To explain, logical xe2x80x9c1""sxe2x80x9d do not normally leak away in a linear fashion. That is, as the voltage in the memory cell drops, the rate of leakage decreases. The improved sensing capability of the present invention allows a smaller voltage to be stored in individual memory cells and still obtain an accurate logical xe2x80x9c1xe2x80x9d detection. The slower rate of leakage in the DVC2 voltage range will also help improve, or increase, the logical xe2x80x9c1sxe2x80x9d refresh period. The refresh period is the amount of time between when a cell containing a logical xe2x80x9c1xe2x80x9d must be refreshed, to account for charge leakage. The required refresh period for a logical xe2x80x9c0xe2x80x9d on the typical cell is not affected much more than reading the zero with no refresh.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.